Accellera Verilog + + Extension assertion construct Requirements Contact Harry

Extension assertion construct Justification: The question arises whether extension assertion constructs are necessary. After all, many Hardware Verification Languages (HVLs) provide powerful language features that can be used to describe correct temporal behavior. These HVLs can be used for data generation and results analysis thru temporal specification. In addition, the Accellera Formal Verification committee is actively defining a property specification language that can be leveraged by multiple verification processes. Therefore, some will say either HVLs or formal Property Languages should be able to provide all the power necessary to express assertions within the design. However, a variety of stakeholders in the design and verification flow necessitates a variety of approaches to specifying design properties.